Raptor-16 Instruction Set

The Raptor-16 Microprocessor Instruction Set consists of six basic instruction types:-

Instruction Type	Mnemonic	Description	Addressing Modes	Condition Codes
Data Movement	Load Move Push Pop	Load Register Move Data Push Registers onto Stack Pop Registers off Stack	Set 1 Set 2 - -	CC CC CC CC
Logical Operations	And Or Xor Not Shl Shr	Logical And Logical Or Logical Exclusive Or Logical Invert Shift Left Shift Right	Set 2 Set 2 Set 2 Set 2 Set 2 Set 2	CC CC CC CC CC CC
Arithmetic Operations	Add Sub Mulu* Muls* Divu* Divs*	Add Subtract Unsigned Multiply Signed Multiply Unsigned Divide Signed Divide	Set 2 Set 2 - - - -	CC CC - - - -
Comparison	Cmp	Compare	Set 2	CC
Flow Control	Bra Bsr Rts Rti	Branch Branch to Subroutine Return from Subroutine Return from Interrupt	Set 3 Set 3 - -	CC and BC CC and BC - -
Others	Nop	No Operation	-	-

Raptor-16 executes all its instructions using 16-bit computation, hence all Quick Operands are suitably extended by the processor to create a full 16-bit value.

* Not Supported in Release 1 of Raptor-16 (they were too big to fit in my Spartan!).

Load Instruction

Description:

Load the source operand (immediate data) into the destination operand (register).

Assembler:	LoadQ	#n,Dn
	LoadQ	#n,An
	LoadQ	#n,SP
	LoadQ	#n,PC

Addressing Modes: Set 1

Condition Codes: CC

Notes:

When using immediate data out of the range -128 to 127 use Move instead.

Examples:	LoadQ	#-1,D1	; Move the value -1 into D1.
	LoadQ	#127,A5	; Move the value 127 into A5.
	LoadQ	#-128,A3	; Move the value -128 into A3.
	LoadQ	#$0000,D7	; Move the value 0 into D7.

Move Instruction

Description:

Move the source operand (contents) to the destination operand (location).

Assembler:	MoveQ	#n,<dst>
	Move	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between -8 and 7 use MoveQ instead of Move to improve code density.

Examples:	MoveQ	#-1,A4	; Move the value -1 into A4.
	MoveQ	#0,4(A2)	; Move the value 0 into the memory location pointed at by A2, offset by 4.
	Move	60,20	; Move the contents of memory location 60 into memory location 20.
	Move	D2,-(Sp)	; Move the contents of D2 onto the Stack.

Push Instruction

Description:

Push a collection of registers (content) onto the stack (location).

Assembler:	PushL	<Register Set 1>
	PushU	<Register Set 2>

Register Set 1: Any or all registers from the set D0, D1, D2, D3, A0, A1, A2 and A3.

Register Set 2: Any or all registers from the set D4, D5, D6, D7, A4, A5, SP and PC.

Condition Codes: CC (the last register pushed sets the condition codes)

Notes:

The Registers are pushed in the order shown above, D0/D4 first and A3/PC last.

Examples:	PushL	D0,A2,D3	; Pushes D0, D3 and A2 onto the stack in that order.
	PushU	A4,D7,A5,D6	; Pushes D6, D7, A4 and A5 onto the stack in that order.
	PushL	D0	; Pushes D0 onto the stack.
	PushU	D4,D7,D6,D5	; Pushes D4, D5, D6 and D7 onto the stack in that order.

Pop Instruction

Description:

Pop a collection of registers (content) off the stack (location).

Assembler:	PopL	<Register Set 1>
	PopU	<Register Set 2>

Notes:

The Registers are popped in the reverse order shown above, A3/PC first and D0/D4 last.

Examples:	PopL	D0,A2,D3	; Pops A2, D3 and D0 off the stack in that order.
	PopU	A4,D7,A5,D6	; Pops A5, A4, D7 and D6 off the stack in that order.
	PopL	D0	; Pops D0 off the stack.
	PopU	D4,D7,D6,D5	; Pops D7, D6, D5 and D4 off the stack in that order.

And Instruction

Description:

Logical AND the source operand (contents) with the destination operand (contents) and write the result back to the destination operand (location).

Assembler:	AndQ	#n,<dst>
	And	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between -8 and 7 use AndQ instead of And to improve code density.

Examples:	AndQ	#1,D3	; Logical AND the value 1 to D3.
	AndQ	#$FFF8,-3(A5)	; Logical AND the value $FFF8 to the memory location pointed at by A5, offset by -3.
	And	$400,$401	; Logical AND the contents of memory location $400 to memory location $401.
	And	A3,(A0)	; Logical AND the contents of A3 to the memory location pointed at by A0.

Or Instruction

Description:

Logical OR the source operand (contents) with the destination operand (contents) and write the result back to the destination operand (location).

Assembler:	OrQ	#n,<dst>
	Or	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between -8 and 7 use OrQ instead of Or to improve code density.

Examples:	OrQ	#%110,A4	; Logical OR the value %110 to A4.
	OrQ	#$FFF6,(A3)	; Logical OR the value $FFF6 to the memory location pointed at by A3.
	Or	$10,D4	; Logical OR the contents of memory location $10 to D4.
	Or	A0,D7	; Logical OR the contents of A0 to D7.

Xor Instruction

Description:

Logical XOR the source operand (contents) with the destination operand (contents) and write the result back to the destination operand (location).

Assembler:	XorQ	#n,<dst>
	Xor	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between -8 and 7 use XorQ instead of Xor to improve code density.

Examples:	XorQ	#$FFFF,(A1)	; Logical XOR the value $FFFF to the memory location pointed at by A1.
	XorQ	#%1,D3	; Logical XOR the value %1 to D3.
	Xor	$51,$13	; Logical XOR the contents of memory location $51 to memory location $13.
	Xor	(A3),A5	; Logical XOR the contents of the memory location pointed at by A3 to A5.

Not Instruction

Description:

Logically invert the destination operand (contents) and write the result back to the destination operand (location).

Assembler:

Not

<dst>

Notes:

The implementation for this instruction is; XorQ #$FFFF,<dst>. See Xor for further details.

Shl Instruction

Description:

Logically shift left the destination operand (contents) by the source operand (contents) and write the result back to the destination operand (location).

Assembler:	ShlQ	#n,<dst>
	Shl	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between 0 and 15 use ShlQ instead of Shl to improve code density.
Only the least four significant bits of the source operand are used to make up the shift amount (0 to 15).

Examples:	ShlQ	#1,P4	; Shift the contents of Port 4 left by 1.
	ShlQ	#8,2(A3)	; Shift the contents of the memory location pointed at by A3, offset by 2 left by 8.
	Shl	D3,A4	; Shift the contents of A4 left by the amount in D3.
	Shl	$16,D2	; Shift the contents of D2 left by the amount in memory location $16.

Shr Instruction

Description:

Logically shift right the destination operand (contents) by the source operand (contents) and write the result back to the destination operand (location).

Assembler:	ShrQ	#n,<dst>
	Shr	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between 0 and 15 use ShrQ instead of Shr to improve code density.
Only the least four significant bits of the source operand are used to make up the shift amount (0 to 15).

Examples:	ShrQ	#1,(A4)	; Shift the memory location pointed at by A4 right by 1.
	ShrQ	#10,D2	; Shift the contents of D2 right by 10.
	Shr	A4,$18	; Shift the contents of memory location $18 right by the amount in A4.
	Shr	$28,$32	; Shift the contents of memory location $32 right by the amount in memory location $28.

Add Instruction

Description:

Add the source operand (contents) to the destination operand (contents) and write the result back to the destination operand (location).

Assembler:	AddQ	#n,<dst>
	Add	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between 0 and 15 use AddQ instead of Add to improve code density.

Examples:	AddQ	#1,(A5)	; Add the value 1 to the memory location pointed at by A5.
	AddQ	#15,D0	; Add the value 15 to D0.
	Add	A5,$30	; Add the contents of A5 to memory location $30.
	Add	$20,(A2)	; Add the contents of the memory location $20 to the memory location pointed at by A2.

Sub Instruction

Description:

Subtract the source operand (contents) from the destination operand (contents) and write the result back to the destination operand (location).

Assembler:	SubQ	#n,<dst>
	Sub	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between 0 and 15 use SubQ instead of Sub to improve code density.

Examples:	SubQ	#2,(A0)	; Subtract the value 2 from the memory location pointed at by A0.
	SubQ	#12,D1	; Subtract the value 12 from D1.
	Sub	D4,D2	; Subtract the contents of D4 from D2.
	Sub	#255,$20	; Subtract the value 255 from the memory location $20.

Cmp Instruction

Description:

Subtract the source operand (contents) from the destination operand (contents) and set the condition codes accordingly. No results are written back to the destination operand (location)

Assembler:	CmpQ	#n,<dst>
	Cmp	<src>,<dst>

Addressing Modes: Set 2

Condition Codes: CC

Notes:

When using immediate data between -8 and 7 use CmpQ instead of Cmp to improve code density.

Examples:	CmpQ	#-1,$10(A3)	; Compare the value -1 to the memory location pointed at by A3, offset by $10.
	CmpQ	#7,D6	; Compare the value 7 to that of D6.
	Cmp	A4,A0	; Compare the contents of A4 to that of A0.
	Cmp	#65,(A3)	; Compare the value 65 to the memory location pointed at by A3.

Bra Instruction

Description:

Branch to the destination operand (contents) if the specified condition is met, otherwise execute the next instruction.

Assembler:	BraQ	<condition>,Label
	BraQ	<condition>,#n
	Bra	<condition>,<dst>

Branch Conditions: BC

Addressing Modes: Set 3

Condition Codes: Unaffected.

Notes:

When using PC Relative data between -64 and 127 use BraQ instead of Bra to improve code density.
When using an Immediate Address between 0 and 7 use BraQ instead of Bra to improve code density.
When using the -(An) or (An)+ modes the register is only decreased or increased if the branch is taken.
When using Bra/BraQ alw,<dst> the "alw," part can be omitted.

Examples:	BraQ	Here	; Branch to the code labelled by 'Here'.
	BraQ	zrs,There	; Branch to the code labelled by 'There' if the Zr Condition is set.
	Bra	soc,#$400	; Branch to the immediate address $400 if the So Condition is clear.
	Bra	#Everywhere	; Branch to the immediate address labelled by 'Everywhere'.

Bsr Instruction

Description:

Branch to the destination operand (contents) and push the address of the next instruction onto the stack if the specified condition is met, otherwise execute the next instruction.

Assembler:	BraQ	<condition>,Label
	BraQ	<condition>,#n
	Bra	<condition>,<dst>

Branch Conditions: BC

Addressing Modes: Set 3

Condition Codes: Unaffected.

Notes:

When using PC Relative data between -64 and 127 use BsrQ instead of Bsr to improve code density.
When using an Immediate Address between 0 and 7 use BsrQ instead of Bsr to improve code density.
When using the -(An) or (An)+ modes the register is only decreased or increased if the branch is taken.
Every Bsr/BsrQ call should ultimately be terminated by a Rts call (Return from Subroutine).
When using Bsr/BsrQ alw,<dst> the "alw," part can be omitted.

Examples:	BsrQ	D5	; Branch to the memory address held in D5.
	BsrQ	uoc,#$30	; Branch to the immediate address $30 if the Uo Condition is clear.
	Bsr	sos,Here	; Branch to the code labelled by 'Here' if the So Condition is set.
	Bsr	SubA	; Branch to the code labelled by 'SubA'.

Rts Instruction

Description:

If the specified condition is met the return address is popped off the stack and then branched to, otherwise the next instruction is executed.

Assembler:

Rts

Notes:

The implementation for this instruction is; Bra <condition>,(Sp)+. See Bra for further details.
When using Rts alw the "alw" part can be omitted.

Rti Instruction

Description:

Returns from an interrupt routine by restoring the Program Counter and Control Register stored on the stack.

Assembler:

Rti

Nop Instruction

Description:

No-Operation. Do Nothing but move on to execute the next instruction.

Assembler:

Nop

Notes:

The implementation for this instruction is; Label BraQ nev,Label. See Bra for further details.

Load Addressing Modes

Addressing Mode		Source Operand	Destination Operand
Description	Syntax	Source Operand	Destination Operand
Register Direct	Dn, An, Sp or Pc
Register Indirect	(An), (Sp) or (Pc)
Register Indirect with Pre-Decrement	-(An), -(Sp) or -(Pc)
Register Indirect with Post-Increment	(An)+, (Sp)+ or (Pc)+
Register Indirect with Displacement	d(An), d(Sp) or d(Pc)
Immediate Quick (Address/Data)	#n or #Label
Port Direct	Pn
Control Register Direct	CR
Immediate (Address/Data)	#n or #Label
Address Direct	n or Label
PC Relative Quick	Label
PC Relative	Label

Permitted Ranges:

An
Dn
#n

n = 0 to 5
n = 0 to 7
n = -128 to 127 [Immediate Quick]

Move, And, Or, Xor, Shl, Shr, Add, Sub & Cmp Addressing Modes

Addressing Mode		Source Operand	Destination Operand
Description	Syntax	Source Operand	Destination Operand
Register Direct	Dn, An, Sp or Pc
Register Indirect	(An), (Sp) or (Pc)
Register Indirect with Pre-Decrement	-(An), -(Sp) or -(Pc)
Register Indirect with Post-Increment	(An)+, (Sp)+ or (Pc)+
Register Indirect with Displacement	d(An), d(Sp) or d(Pc)
Immediate Quick (Address/Data)	#n or #Label
Port Direct	Pn
Control Register Direct	CR
Immediate (Address/Data)	#n or #Label
Address Direct	n or Label
PC Relative Quick	Label
PC Relative	Label

Permitted Ranges:

An
Dn
Pn
d
#n
#n
#n
n

n = 0 to 5
n = 0 to 7
n = 0 to 4
d = -32768 to 32767
n = -8 to 7 (Move, And, Or, Xor & Cmp) [Immediate Quick]
n = 0 to 15 (Shl, Shr, Add & Sub) [Immediate Quick]
n = -32768 to 65535 [Immediate]
n = 0 to 65535 [Address Direct]

Bra & Bsr Addressing Modes

Addressing Mode		Destination Operand
Description	Syntax	Destination Operand
Register Direct	Dn, An, Sp or Pc
Register Indirect	(An), (Sp) or (Pc)
Register Indirect with Pre-Decrement	-(An), -(Sp) or -(Pc)
Register Indirect with Post-Increment	(An)+, (Sp)+ or (Pc)+
Register Indirect with Displacement	d(An), d(Sp) or d(Pc)
Immediate Quick (Address/Data)	#n or #Label
Port Direct	Pn
Control Register Direct	CR
Immediate (Address/Data)	#n or #Label
Address Direct	n or Label
PC Relative Quick	Label
PC Relative	Label

Permitted Ranges:

An
Dn
Pn
d
#n
#n
n

n = 0 to 5
n = 0 to 7
n = 0 to 4
d = -32768 to 32767
n = 0 to 7 [Immediate Quick]
n = -32768 to 65535 [Immediate]
n = 0 to 65535 [Address Direct]

Condition Codes

Raptor-16 has four Conditions Codes that are affected by all instructions other than Bra, Bsr, Rts, Rti, Nop and any other instruction that modifies the Program Counter. These Condition Codes are detailed below, along with a description of the circumstances in which they are effected.

Code	Description
Zr	Zero	Set if the result is zero, otherwise cleared.
Ng	Negative	Set if the result is negative, otherwise cleared.
Uo	Unsigned Overflow	Set if the unsigned result is out of the range 0 to 65535, otherwise cleared.
So	Signed Overflow	Set if the signed result is out of the range -32768 to 32767, otherwise cleared.

The term 'result' refers to the result of the instruction that has just been executed. If the instruction is a Move or a Load then 'result' refers to the data being moved or loaded.

Note that the logical operations And, Or, Xor, Shl and Shr all clear the So and Uo Condition Codes, as it would be meaningless to to anything else.

Branch Conditions

Condition Codes are used by the instructions Bra and Bsr to determine if a branch should be taken. If a Branch Condition is met then a branch is taken, otherwise it is not. These Branch Conditions are detailed below.

General Branch Conditions:

Condition	Description	Test
alw	Always Branch	1
nev	Never Branch	0
zrs	Branch if Zero Condition is set	Zr
zrc	Branch if Zero Condition is clear	NOT(Zr)
ngs	Branch if Negative Condition is set	Ng
ngc	Branch if Negative Condition is clear	NOT(Ng)
uos	Branch if Unsigned Overflow Condition is set	Uo
uoc	Branch if Unsigned Overflow Condition is clear	NOT(Uo)
sos	Branch if Signed Overflow Condition is set	So
soc	Branch if Signed Overflow Condition is clear	NOT(So)

Branch Conditions relating mainly to Cmp S,D and Sub S,D:

Condition	Description	Test
equ	Branch if D is equal to S (Unsigned/Signed)	Zr
neq	Branch if D is not equal to S (Unsigned/Signed)	NOT(Zr)
ugt	Branch if D is greater than S (Unsigned)	NOT(Uo OR Zr)
uge	Branch if D is greater than or equal to S (Unsigned)	NOT(Uo)
ult	Branch if D is less than S (Unsigned)	Uo
ule	Branch if D is less than or equal to S (Unsigned)	Uo OR Zr
sgt	Branch if D is greater than S (Signed)	NOT((So XOR Ng) OR Zr)
sge	Branch if D is greater than or equal to S (Signed)	NOT(So XOR Ng)
slt	Branch if D is less than S (Signed)	So XOR Ng
sle	Branch if D is less than or equal to S (Signed)	(So XOR Ng) OR Zr

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