Digital Video Pipeline

The Digital Video Pipeline provides a very modular way of connecting together any number of video circuits. Its unique pipelined structure also provides an inherent way of overlaying video.

The basic building block (pipe-section) of a pipeline is shown below.

Clk - 27MHz video clock
Rst - Synchronous Reset
En - Enable Function
Video - 8-bit Digital Video Stream
TOF - Top of Frame (pulsed at the start of each frame)
Line - 10-bit Line Number (PAL = 0-575, NTSC = 0-479)
Sample - 11-bit Line Position (PAL & NTSC = 0-1439)
FVH - 3-bit Information Vector
- F - Field (Field 1 = '0', Field 2 = '1')
- V - Vertical Blanking (Not Blanking = '0', Blanking = '1')
- H - Horizontal Blanking (Not Blanking = '0', Blanking = '1')

The "digital video" that this page refers to is Standard Definition BT656 YCbCr (4:2:2). A brief introduction to this standard is available here if required.

Listed below are some real world examples of the Digital Video Pipeline in action.

Example 1 - Blank Screen Generator

This example shows how a single stage pipeline can be used to create a blue screen.

Example 2 - Colour Bar/Block Generator

This example shows how a three stage pipeline can be used to create a colour bar or colour block test pattern.

By controlling the Pipe-Section Enables three possible video outputs can be generated:-

A single colour blank screen
A colour bar test pattern
A colour block test pattern

Example 3 - Moving Object Overlay

This example shows how a four stage pipeline can be used to overlay two separate objects.

By controlling the Pipe-Section Enables six possible video outputs can be generated:-

A single colour blank screen
A colour bar test pattern
A blank screen with one moving rectangle
A colour bar screen with one moving rectangle
A blank screen with two moving rectangles
A colour bar screen with two moving rectangles

Example 4 - Live Video Overlay

By replacing the Blank Screen module in the above examples with the Video Lock module live video overlay can easily be achieved. This example shows how the Video Lock module is used.

Design Source

Details of the design source used in the above examples is given below:-

blank_screen_top.vhd - Top level wrapper for Example 1.

colour_bars_top.vhd - Top level wrapper for Example 2.

bouncy_rectangle_top.vhd - Top level wrapper for Example 3.

blank_screen.vhd - Build and output a full frame of digital video that is floodfilled with one colour.

colour_bars.vhd - Overlay a colour bar test pattern on the incoming video stream and output the result.

colour_blocks.vhd - Overlay a colour block test pattern on the incoming video stream and output the result.

bouncy_rectangle.vhd - Overlay a moving rectangle on the incoming video stream and output the result.

The design source and top level modules for all the above examples can be found in the following zip:-

video.zip

Although the VHDL source code (intellectual property) is targeted towards a Xilinx FPGA its low-level RTL implementation ensures an optimal result for any ASIC or FPGA architecture.

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